1. Field of the Invention
Generally, the present disclosure relates to the fabrication of sophisticated integrated circuits including complex layer stacks, such as gate layer stacks of highly capacitive gate structures formed on the basis of a high-k gate dielectric and metal-containing electrode materials.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. During the very complex fabrication process, typically, material systems have to be formed and patterned, for instance, by wet chemical processes and plasma assisted etch processes, wherein usually one or more material layers may be provided as sacrificial layers, while other materials may represent permanent materials in the form of conductive, dielectric and semiconductive materials. The patterning process typically relies on the different etch rates of the materials with respect to an appropriate etch recipe such that a desired pattern may be transferred from a lithography mask into the material system under consideration. For example, a plurality of organic materials, such as photoresist materials and the like, may have a reduced etch rate compared to the plurality of materials that are typically used in the semiconductor fabrication process. Moreover, well-established dielectric materials, such as silicon dioxide based dielectrics and silicon nitride based dielectrics, may be provided with varying material characteristics, so that efficient etch stop capabilities may be provided on the basis of these materials in situations when superior integrity in view of elevated temperatures and the like is required. For example, a plurality of wet chemical etch recipes and plasma assisted etch recipes are available in which silicon dioxide and silicon nitride may be selectively etched by using the other material as an etch stop. Upon continuously reducing the feature sizes of circuit elements, however, the material systems may have to be provided with reduced thickness and additional complex processes may have to be applied, thereby resulting in an undue interaction of aggressive process environments with the delicate layers.
One prominent example of patterning a delicate layer system is the formation of gate electrode structures of sophisticated field effect transistors, which represent one important type of circuit element that substantially determines performance of complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of transistors, e.g., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Consequently, the process of patterning a gate electrode structure may require very sophisticated process techniques, beginning from the deposition of appropriate material layers, such as gate dielectrics, the silicon material which may typically be used as an electrode material, followed by the deposition of any further materials, such as hard mask materials, anti-reflective coating (ARC) materials and the like, which may be required for patterning the gate electrode material according to the specified design rules. For example, in highly sophisticated semiconductor devices, the gate length may be 50 nm and less, which may thus also impose tightly set process margins on the processes involved and also on the defect rate, for instance with respect to particle contamination and the like. For example, a typical process sequence for forming a gate electrode structure having critical dimensions in the above-specified range may comprise the following processes. First, an appropriate gate dielectric material may be formed, for instance on the basis of silicon dioxide and the like, followed by the deposition of the silicon electrode material, for instance in the form of amorphous silicon or polysilicon, which may be accomplished by using sophisticated low pressure chemical vapor deposition (CVD) techniques and the like. Thereafter, appropriate hard mask materials, such as amorphous carbon, silicon oxynitride and the like, possibly in combination, may typically be used in many approaches in order to obtain a precise patterning of an etch mask on the basis of sophisticated photoresist materials. Next, a sophisticated lithography process is performed in order to obtain a resist mask, which may be used for patterning the hard mask material or materials, wherein, during the corresponding patterning process, the resist material may be substantially consumed or may be removed in a subsequent removal process. Thereafter, the hard mask may be further treated, if required, for instance in order to obtain the desired critical dimension, and subsequently the gate electrode material, i.e., the silicon material, may be etched on the basis of highly selective etch chemistries on the basis of, for instance, hydrogen bromide and the like. The etch process may be stopped on and in the gate dielectric material which may have a thickness of 1.5 to several nanometers, depending on the device requirements, and may be thus precisely controlled at least in a final phase of the etch process. During the patterning process, the plasma assisted etch ambient is appropriately established, for instance, on the basis of polymer additives, in order to obtain the desired anisotropic etch behavior, which may provide substantially vertical sidewall surfaces of the resulting gate electrode structure. Thereafter, the hard mask material may be removed by appropriate etch recipes. Generally, in various manufacturing stages, the resulting surface of a semiconductor device may have to be cleaned, for instance, in view of undesired material residues, such as oxides and the like, as well as other contaminants in the form of organic contaminants, metal residues and the like. In particular, prior to or after critical process sequences, an efficient cleaning of the surface has to be performed. Thus, after patterning the gate electrode structure, the further processing may involve efficient cleaning recipes in view of removing any organic or metallic contaminants which may have been formed during the preceding complex patterning sequence, in particular when approaches including various hard mask materials and a corresponding patterning thereof are to be used in forming the gate electrode structure. For example, a plurality of wet chemical cleaning recipes are available, wherein some very efficient ones of these recipes may be based on aggressive chemicals, such as hydrofluoric acid (HF), which may efficiently attack silicon oxide and may thus also efficiently remove any contaminants adhering to the silicon oxide or embedded therein. Consequently, after the critical gate patterning process and after an efficient wet chemical cleaning process based on HF, the further processing may be continued by forming other basic components of field effect transistors, such as drain and source areas.
Due to the very reduced critical dimensions of transistor elements, resulting in a gate length of 50 nm and less, however, a further gain in performance may be difficult to achieve since the controllability of a short channel length associated with the reduced gate length typically requires, among other things, an appropriate adaptation of the thickness of the gate dielectric material, which, however, may result, in addition to increased process complexity in view of depositing the gate dielectric material and patterning the silicon gate electrode material, in a very pronounced increase of leakage currents, as the charge carriers may readily tunnel into and through the very thin silicon dioxide based gate dielectric material. In order to further enhance overall transistor performance without further increasing the dynamic and static leakage currents of gate electrode structures, other mechanisms have been proposed. For this purpose, the strain in the channel region may be modified, which may result in a modified charge carrier mobility. Consequently, by applying an appropriate strain component, the charge carrier mobility of electrons and holes, respectively, may be increased for a given crystallographic configuration of the silicon-based channel region. In this way, a strained silicon material may be considered as a “new” type of semiconductor material that allows the fabrication of fast and powerful semiconductor devices without requiring an even further reduced thickness of the gate dielectric material.
One very efficient mechanism is the incorporation of a strained silicon/germanium semiconductor alloy in the drain and source regions of P-channel transistors in order to create a compressive strain component in the channel region, thereby increasing hole mobility and thus the drive current of the transistor. The incorporation of the strain-inducing silicon/germanium material is typically accomplished by forming cavities laterally adjacent to the gate electrode structure and filling the cavities with the silicon/germanium alloy on the basis of a selective epitaxial growth technique. During the corresponding process sequence, the delicate gate electrode structure is to be reliably masked to avoid undue etch damage and also to avoid material deposition during the selective epitaxial growth process, which may otherwise result in non-acceptable irregularities during the further processing of the device.
To this end, typically, a cap material in the form of a silicon nitride material is formed above the polysilicon gate electrode material and is patterned together with the silicon material in order to provide a gate electrode structure having a silicon nitride cap layer on its top surface. Moreover, a silicon nitride sidewall spacer may be formed to reliably cover the sidewalls of the delicate gate electrode structure during the etch process and the subsequent selective epitaxial growth process. However, upon removing the cap material and the sidewall spacers, etch-related irregularities may be induced, as will be described with reference to the following drawings.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, such as a silicon substrate and the like, above which is formed a silicon-based semiconductor layer 102. Moreover, a gate electrode structure 151 is formed on the semiconductor layer 102 and comprises a gate insulation layer 151B, which separates a silicon material, such as a polysilicon material 151A, from a channel region 152. Furthermore, the gate electrode structure 151 comprises a silicon nitride cap layer 151C, as discussed above. Additionally, sidewall spacers 103 are formed on sidewalls of the gate electrode structure 151. Furthermore, in the manufacturing stage shown, a silicon/germanium alloy 153 is formed in the semiconductor layer 102 laterally offset from the gate electrode structure 151 by the spacers 103.
It should be appreciated that the semiconductor device 100 as illustrated in FIG. 1a may be formed in accordance with process techniques described above, i.e., the gate electrode structure 151 may be formed by providing the gate insulation layer 151B followed by the polysilicon material 151A in combination with the silicon nitride cap layer 151C, followed by the deposition of appropriate hard mask materials which are then patterned to form an etch mask in order to pattern the layer stack 151B, 151A, 151C. Thereafter, appropriate wet chemical cleaning processes are performed as discussed above and the spacers 103 may be formed, for instance, by depositing a silicon nitride material and anisotropically etching the same in order to provide the spacers 103. Thereafter, cavities may be formed and may be subsequently filled with the silicon/germanium material 153 on the basis of a selective epitaxial growth technique, in which a significant material deposition on dielectric surface areas may be efficiently suppressed. Consequently, during etching the cavities and depositing the material 153, the cap layer 151C in combination with the spacer 103 may maintain integrity of the gate electrode structure 151.
FIG. 1b schematically illustrates the semiconductor device 100 during a wet chemical etch process 104 that may be performed on the basis of hot phosphoric acid in order to remove the cap layer 151C and the sidewall spacer 103 (see FIG. 1a) selectively to the polysilicon material 151A. Although hot phosphoric acid may exhibit a high etch selectivity with respect to polysilicon material, nevertheless, a certain degree of material erosion or other etch-related irregularities may be caused during the process 104, in particular at a top surface 151S, which may have a significant influence on the resulting defect rate, i.e., gate failures, during the further processing of the device 100, in particular if very sophisticated semiconductor devices are considered. While significant damage of sidewall surfaces of the gate electrode material 151A may be suppressed by providing an appropriate etch stop liner, for instance in the form of a silicon dioxide material, the provision of a corresponding oxide material between the polysilicon material 151A and the cap layer 151C (FIG. 1a) may be less than desirable in sophisticated applications for the following reasons.
FIG. 1c schematically illustrates an alternative, in which the device 100 is shown after patterning the gate electrode structure 151 which includes a silicon dioxide etch stop layer 151D formed by CVD in this alternative. Consequently, after the deposition of the cap layer 151C and any hard mask materials, the patterning sequence has to be adapted so as to take into consideration the presence of the etch stop material 151D, which has to be patterned on the basis of a different etch chemistry compared to the polysilicon material 151A. Thereafter, the device 100 is subjected to an efficient wet chemical cleaning process 105 based on hydrofluoric acid, which, however, may also attack sidewalls of the etch stop material 151D.
FIG. 1d schematically illustrates the device 100 after the preceding wet chemical cleaning process which may cause notches 105N in the etch stop material 151D since, in view of enhanced controllability, the thickness of the layer 151D may not be arbitrarily reduced and may thus be approximately 5 nm and more. The pronounced notches 105N may, however, result in irregularities during the subsequent formation of the sidewall spacers, such as the spacers 103 (FIG. 1a), thereby compromising a reliable coverage of the sidewalls of the polysilicon material 151A at the notches 105N, which in turn may result in an undesired growth of silicon/germanium material.
Furthermore, in sophisticated applications, a further strategy for enhancing transistor performance without increasing the leakage currents due to a very thin gate dielectric material is the replacement of silicon dioxide based gate dielectric materials with a high-k dielectric material, which is to be understood as a dielectric material having a dielectric constant of 10.0 or higher. In this case, a significantly greater physical thickness of an appropriate high-k dielectric material may provide the same or an increased capacitive coupling, thereby maintaining channel controllability without unduly increasing the leakage currents. In this case, a corresponding gate electrode structure may require an even more complex deposition and patterning process sequence due to the provision of high-k dielectric materials, which may exhibit a very pronounced sensitivity with respect to oxygen and the like, thereby typically requiring the deposition of an appropriate cap material, for instance a titanium nitride material and the like. In many approaches, a certain degree of compatibility with conventional gate electrode structures, such as illustrated in FIGS. 1a-1d, may be maintained by providing a polysilicon material or amorphous silicon material as a place-holder material that is replaced by a work function adjusting metal-containing species and a metal gate electrode in a very advanced manufacturing stage. Thus, providing the etch stop layer 151D (FIG. 1c) in order to enhance process uniformity upon removing any silicon nitride based cap materials, which may be used as hard mask material or as cap material when incorporating a silicon/germanium material, may be less than desirable, since the etch stop layer may have to be removed prior to replacing the polysilicon placeholder material, thereby also negatively affecting other silicon dioxide based materials, such as an interlayer dielectric material, which is provided for embedding the gate electrode structure prior to replacing the polysilicon material.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.